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Microchip Technology /ATSAMD51J18A /QSPI /INTENSET

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Interpret as INTENSET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXC)RXC 0 (DRE)DRE 0 (TXC)TXC 0 (ERROR)ERROR 0 (CSRISE)CSRISE 0 (INSTREND)INSTREND

Description

Interrupt Enable Set

Fields

RXC

Receive Data Register Full Interrupt Enable
DRE

Transmit Data Register Empty Interrupt Enable
TXC

Transmission Complete Interrupt Enable
ERROR

Overrun Error Interrupt Enable
CSRISE

Chip Select Rise Interrupt Enable
INSTREND

Instruction End Interrupt Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data